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fbduan/HDLObf

HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.

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fbduan/ExtremeDV_UVM

UVM resource from github, run simulation use YASAsim flow

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fbduan/SuperScalar-RISCV-CPU

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

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fbduan/core_usb_host

Basic USB 1.1 Host Controller for small FPGAs

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fbduan/electronic-wechat

:speech_balloon: A better WeChat on macOS and Linux. Built with Electron by Zhongyi Tong.

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fbduan/Cache-Design-VERILOG

design of a memory sub system with cache memory

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fbduan/delta

A viewer for git and diff output

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fbduan/Speckle-riscv-spec2006

A wrapper for the SPEC CPU2006 benchmark suite.

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fbduan/ultraembedded_ip_cores

Various HDL (Verilog) IP Cores

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fbduan/SM4_CMAC

CMAC based on SM4

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fbduan/usb20dev

USB 2.0 FS Device controller IP core written in SystemVerilog

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fbduan/OpenSSD-OpenChannelSSD

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fbduan/openpiton

The OpenPiton Platform

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fbduan/Power_Optimization

A TCL script for PrimeTime that implements a post-synthesis leakage power minimization procedure, to optimise the power using a fast algorithm (low CPU time) to get the minimum cost (in terms of power and time)

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fbduan/Cosmos-plus-OpenSSD

Cosmos OpenSSD + Hardware and Software source distribution

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fbduan/Python_DataScienceStudyNotes

这个仓库保管从（数据科学学习手札69）开始的所有代码、数据等相关附件内容

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fbduan/ic_flow_platform

IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow contral.

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fbduan/automatic-verilog

automatic-verilog based on vimscript

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fbduan/dash

Data Apps & Dashboards for Python. No JavaScript Required.

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fbduan/Cores-VeeR-EH2