# Cache-Design-VERILOG

**Repository Path**: fbduan/Cache-Design-VERILOG

## Basic Information

- **Project Name**: Cache-Design-VERILOG
- **Description**: design of a memory sub system with cache memory
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2026-01-09
- **Last Updated**: 2026-01-09

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Cache-Design-VERILOG
design of a memory sub system with cache memory

## Specifications
  1. Size                  - 512kB
  2. Mappping              - Direct Mapping
  3. Write Policy          - Write Through
  4. Cache Line Size       - 8 words
  5. No of Cache Lines     - 64
  6. Replacement Algorithm - None
  
  ### Simulation Results (using Isim simulator)
  #### Read data when data not available in cache - Empty cache line 
  ![image 1](https://github.com/damithkawshan/Cache-Design-VERILOG/blob/master/simulation%20results/data%20not%20in%20cache.png)
  #### Read data when data available in cache
  ![image 2](https://github.com/damithkawshan/Cache-Design-VERILOG/blob/master/simulation%20results/data%20in%20cache.png)
   #### Read data when data not available in cache - Tag mismatch
  ![image 3](https://github.com/damithkawshan/Cache-Design-VERILOG/blob/master/simulation%20results/no_data_valid_line.png)
   #### Write data when data not available in cache - Empty cache line 
  ![image 4](https://github.com/damithkawshan/Cache-Design-VERILOG/blob/master/simulation%20results/write_data_not_exist_cline.png)
  #### Write data when data available in cache - Same cache line 
  ![image 5](https://github.com/damithkawshan/Cache-Design-VERILOG/blob/master/simulation%20results/write_data_existing_cache_line_same_addr.png)