Watch 侠影萍踪 / riscv-assembler forked from 刘定东 / riscv-assembler

Watch 侠影萍踪 / yuheng-riscv-soc forked from DENGCHOW / yuheng-riscv-soc

玉衡是一款从零开始写的 RISC-V 内核的处理器，基于 Verilog 硬件设计语言实现，五级流水线设计，支持 RV32IM 指令集，支持中断，支持 RT-Thread Nano 3.1.5

Watch 侠影萍踪 / VeriLearn forked from nick / VeriLearn

verilog基础入门

Watch 侠影萍踪 / EpicSim forked from 芯华章科技股份有限公司 / EpicSim

EpicSim is a Verilog compiler. It is suitable for use as a simulator

Watch 侠影萍踪 / verilog语言教程 forked from hubingbing / verilog语言教程

verilog语言教程

Watch 侠影萍踪 / 基于Quartus_II的个人FPGA及Verilog项目式学习记录 forked from 梨心 / 基于Quartus_II的个人FPGA及Verilog项目式学习记录

用于记录本人FPGA及Verilog入门的仓库，学习基于野火征途系列FPGA开发板。

Watch 侠影萍踪 / demonstration-verilog forked from 刘翔 / demonstration-verilog

一个教学用的verilog项目

Watch 侠影萍踪 / HyperParser

Watch 侠影萍踪 / verilog-ethernet

Watch 侠影萍踪 / netfpga forked from mirrors_NetFPGA / netfpga

NetFPGA 1G infrastructure and gateware