# chisel-empty

**Repository Path**: qturing/chisel-empty

## Basic Information

- **Project Name**: chisel-empty
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 1
- **Created**: 2025-10-11
- **Last Updated**: 2026-01-06

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# chisel-empty

An almost empty chisel project (and adder) as a starting point for hardware design.

To generate Verilog code for the adder execute:
```bash
make
```

Run the tests with:
```bash
make test
```

[//]: # (Cleanup the repository with:)

[//]: # (```bash)

[//]: # (make clean)

[//]: # (```)

# 编译器新增算法支持硬件生成步骤
## 新增算子参数
common/operator.scala      新增dsa算子，设置dsa特征参数
## 新增硬件生成器
generator/xxx_alu.scala     定义dsa的计算模块生成器
generator/DPM_xxx.scala     定义dsa的数据预处理模块生成器
## 修改以下文件
common/element.scala        新增dsa元素
TopModule.scala             新增支持dsa生成的功能
Main.scala                  在算法列表添加dsa名称