# Simple Risc-V32I CPU

**Repository Path**: UnbalancedCat/simple-risc-v32i-cpu

## Basic Information

- **Project Name**: Simple Risc-V32I CPU
- **Description**: Simple Risc-V32I CPU
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 0
- **Created**: 2022-11-06
- **Last Updated**: 2024-04-25

## Categories & Tags

**Categories**: Uncategorized

**Tags**: CPU, RISC, RISC-V, Verilog

## README

No README documentation available for this project.